1. Field of the Invention
The present invention relates to a rendering method and a rendering system in general and more particularly to a rendering method and a rendering system for drawing pixels corresponding to a predetermined graphic by dividing a two-dimensional image coordinate system into N pixel areas in a first direction and M pixel areas in a second direction which is perpendicular to the first direction, i.e. N.times.M pixel areas in total, and by allocating N.times.M computing sections respectively to the N.times.M pixels in each of the divided areas.
2. Description of the Related Art
With the progress of the resent semiconductor technology, the processability of an image processing system is also increasing.
In so-called computer graphics, there is a case when a plurality of two-dimensional graphics (polygons) having a predetermined fundamental shape (e.g. triangle) is used in displaying a three-dimensional object on a display screen.
A rendering process is then implemented on such polygons by a predetermined arithmetic circuit to calculate a value of brightness of each pixel within the polygon and to render the polygon in correspondence to the value of brightness.
Some system for rendering polygons as described above implements the polygon rendering process at high speed by operating a plurality of arithmetic circuits in parallel.
In utilizing such a plurality of rendering circuits, a display screen 71 is divided as shown in FIG. 1 into a same number of areas with the rendering circuits 61 through 64 (four in FIG. 1) so that each rendering circuit implements the rendering process in the corresponding area.
For instance, the rendering circuit 61 implements the rendering process in a quarter of area (area A) at the upper left corner of the display screen 71 and the rendering circuit 62 implements the rendering process in a quarter of area (area B) at the upper right corner of the display screen 71.
Further, the rendering circuit 63 implements the rendering process in a quarter of area (area C) at the lower left corner of the display screen 71 and the rendering circuit 64 implements the rendering process in a quarter of area (area D) at the lower right corner of the display screen 71.
However, when the display screen is divided as such, there has been a problem that when a polygon to be rendered is contained only within an area allocated to any one of the rendering circuits for example, a time required for processing it is not shortened even though the plurality of rendering circuits are provided because the rendering process is implemented on the polygon only by that one rendering circuit.
There has been also another problem that although it is conceivable to implement an interleave process for implementing the rendering process by allocating pixels per predetermined number to each rendering circuit, it is difficult to render in the definition of sub-pixel level.